Fix wrong MIDR_EL1 value for Neoverse E1

Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h
index 7084604806a7024490af14958df65016a06fb351..96b4661dbe5a0f96c038b6df8e4a3a6e63a14d78 100644 (file)
--- a/include/lib/cpus/aarch64/neoverse_e1.h
+++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -9,7 +9,7 @@
 
 #include <lib/utils_def.h>
 
-#define NEOVERSE_E1_MIDR               U(0x410FD060)
+#define NEOVERSE_E1_MIDR               U(0x410FD4A0)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions.